ReddRadar
Topic: agentic-workflow
2,980 skills in this topic.
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waterfall-calculator
Calculates distribution waterfalls per LPA terms, carry, clawback
a5c-ai/babysitter 514
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axi-protocol
Expert skill for AMBA AXI protocol implementation and verification in FPGA designs
a5c-ai/babysitter 514
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cdc-analysis
Specialized skill for clock domain crossing analysis and synchronizer design in FPGA designs
a5c-ai/babysitter 514
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formal-verification
Formal property verification and model checking skill for FPGA designs
a5c-ai/babysitter 514
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fpga-debugging
On-chip debugging skill with ILA, VIO, and related FPGA debug tools
a5c-ai/babysitter 514
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fsm-design
Specialized skill for finite state machine design and optimization in FPGAs
a5c-ai/babysitter 514
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hdl-simulation
Multi-simulator expertise for functional verification of FPGA designs
a5c-ai/babysitter 514
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hls-cpp-to-rtl
Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools
a5c-ai/babysitter 514
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ip-core-management
Vendor IP core configuration and integration expertise for FPGA designs
a5c-ai/babysitter 514
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memory-interfaces
Expert skill for on-chip and external memory interface design in FPGAs
a5c-ai/babysitter 514
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place-and-route
Expert skill for FPGA place and route optimization and physical implementation
a5c-ai/babysitter 514
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power-analysis
FPGA power estimation and optimization skill for low-power design
a5c-ai/babysitter 514
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rtl-linting
RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.
a5c-ai/babysitter 514
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sva-assertions
Specialized skill for creating and debugging SystemVerilog assertions for FPGA verification
a5c-ai/babysitter 514
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synthesis-optimization
Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.
a5c-ai/babysitter 514
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timing-constraints
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
a5c-ai/babysitter 514
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uvm-methodology
Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification
a5c-ai/babysitter 514
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verilog-sv-language
Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.
a5c-ai/babysitter 514
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vhdl-language
Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.
a5c-ai/babysitter 514
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dns-protocol
Expert skill for DNS protocol implementation, configuration, and service discovery
a5c-ai/babysitter 514
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event-loop
Expert skill for high-performance event-driven I/O programming and optimization
a5c-ai/babysitter 514
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grpc-protocol
Expert skill for gRPC protocol implementation, debugging, and performance optimization
a5c-ai/babysitter 514
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http-protocol
Deep HTTP/1.1, HTTP/2, and HTTP/3 protocol expertise for web protocol implementation and compliance
a5c-ai/babysitter 514
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load-balancer
Expert skill for load balancer configuration, algorithms, and high availability design
a5c-ai/babysitter 514