ReddRadar
Topic: agent-orchestration
2,114 skills in this topic.
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verilog-sv-language
Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.
a5c-ai/babysitter 514
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uvm-methodology
Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification
a5c-ai/babysitter 514
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stakeholder-crm
Stakeholder relationship management and engagement tracking
a5c-ai/babysitter 514
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speaking-events
Speaking opportunity discovery and conference management
a5c-ai/babysitter 514
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social-listening-pr
Social media monitoring and conversation analysis for PR intelligence
a5c-ai/babysitter 514
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reputation-intelligence
Reputation measurement and benchmarking platform integration
a5c-ai/babysitter 514
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press-release-distribution
Wire service integration and press release distribution management
a5c-ai/babysitter 514
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pr-analytics
PR measurement and reporting automation following Barcelona Principles with comprehensive analytics and visualization capabilities
a5c-ai/babysitter 514
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media-training-simulation
Media interview preparation and crisis simulation tools for executive readiness and spokesperson development
a5c-ai/babysitter 514
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media-monitoring
Deep integration with media monitoring platforms for coverage tracking, sentiment analysis, and reporting
a5c-ai/babysitter 514
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media-database
Journalist database access and media outreach automation
a5c-ai/babysitter 514
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investor-relations-platform
Investor communications and financial disclosure management for public company stakeholder relations
a5c-ai/babysitter 514
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internal-comms-platform
Employee communications platform integration and analytics
a5c-ai/babysitter 514
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influencer-kol-management
Industry influencer and key opinion leader relationship management
a5c-ai/babysitter 514
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timing-constraints
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
a5c-ai/babysitter 514
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power-analysis
FPGA power estimation and optimization skill for low-power design
a5c-ai/babysitter 514
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rtl-linting
RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.
a5c-ai/babysitter 514
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sva-assertions
Specialized skill for creating and debugging SystemVerilog assertions for FPGA verification
a5c-ai/babysitter 514
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synthesis-optimization
Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.
a5c-ai/babysitter 514
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benefits-tracking-dashboard
Track and visualize benefit realization against targets
a5c-ai/babysitter 514
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critical-path-analyzer
Perform critical path method (CPM) analysis with forward/backward pass calculations
a5c-ai/babysitter 514
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change-request-analyzer
Analyze change request impacts on scope, schedule, and cost
a5c-ai/babysitter 514
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place-and-route
Expert skill for FPGA place and route optimization and physical implementation
a5c-ai/babysitter 514
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agile-metrics-calculator
Calculate and analyze Agile delivery metrics including velocity, burndown, and flow metrics
a5c-ai/babysitter 514