EMC Pre-Compliance Skill

Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.

This is a risk analyzer, not a compliance predictor. It catches ~70% of common EMC design mistakes before fabrication. It cannot guarantee FCC/CISPR compliance — only a calibrated measurement in an accredited lab can do that. But it can reduce the first-spin failure rate from ~50% toward ~20-30%, potentially saving $5K-$50K per avoided board respin.

Related Skills

Handoff guidance: Run the kicad skill's analyze_schematic.py and analyze_pcb.py first — this skill consumes their JSON output. Use --full on the PCB analyzer for best results (enables per-track coordinates for ground plane crossing, edge proximity, and return path checks). During a design review, run EMC analysis after the schematic/PCB analyzers and SPICE simulation, then incorporate EMC findings into the report.

Requirements

• Python 3.8+ — stdlib only, no pip dependencies
• Schematic analyzer JSON — from analyze_schematic.py --output
• PCB analyzer JSON — from analyze_pcb.py --full --output (recommended with --full)
• SPICE simulator (optional) — ngspice, LTspice, or Xyce for SPICE-enhanced PDN/filter checks. Auto-detected. Without one, analytical models run unchanged.

Workflow

Step 1: Run the analyzers

python3 <kicad-skill-path>/scripts/analyze_schematic.py design.kicad_sch --output schematic.json
python3 <kicad-skill-path>/scripts/analyze_pcb.py design.kicad_pcb --full --output pcb.json

Step 2: Run EMC analysis

# Full analysis (both schematic and PCB)
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --output emc.json

# SPICE-enhanced (improved PDN and filter accuracy)
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --spice-enhanced

# Select target standard
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --standard cispr-class-b

# Select target market (sets all applicable standards)
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --market eu

# Filter by severity
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --severity high

# Human-readable text output
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --text

Step 3: Interpret results

Read the JSON report and incorporate findings into the design review. Each finding has a severity, rule ID, description, and actionable recommendation. See "Interpreting Results" below.

What Gets Checked

42 rule IDs across 17 categories. Each rule has a specific threshold, rationale, and source citation — see references/pcb-emc-rules.md for full details.

Advisory outputs (not findings):

• Pre-compliance test plan — frequency band prioritization, interface risk ranking, near-field probe points
• Regulatory coverage — market-to-standards mapping, coverage matrix (what the tool checks vs what requires lab testing)

Output Format

{
  "summary": {
    "total_checks": 42,
    "critical": 2, "high": 5, "medium": 8, "low": 12, "info": 15,
    "emc_risk_score": 73
  },
  "target_standard": "fcc-class-b",
  "findings": [
    {
      "category": "ground_plane",
      "severity": "CRITICAL",
      "rule_id": "GP-001",
      "title": "Signal crosses ground plane void",
      "description": "Net SPI_CLK crosses a 3.2mm gap in GND on In1.Cu",
      "components": ["U3", "U7"],
      "nets": ["SPI_CLK"],
      "recommendation": "Route around the gap, or fill the void"
    }
  ],
  "per_net_scores": [
    {"net": "SPI_CLK", "score": 67, "finding_count": 3, "rules": ["GP-001", "CK-001", "BE-001"]}
  ],
  "test_plan": {
    "frequency_bands": [{"band": "30-88 MHz", "risk_level": "high", "source_count": 12}],
    "interface_risks": [{"connector": "J1", "protocol": "USB", "risk_score": 8}],
    "probe_points": [{"ref": "L1", "x": 45.2, "y": 32.1, "reason": "switching inductor"}]
  },
  "regulatory_coverage": {
    "market": "us",
    "applicable_standards": ["FCC Part 15 Class B"],
    "coverage_matrix": [{"standard": "...", "coverage": "partial", "note": "..."}]
  }
}

Severity Levels

Risk Score

Each rule ID contributes at most 3 findings to the score (worst severity first). This prevents per-net rules like GP-001 from saturating the score on 2-layer boards. All findings are still reported — only the score is capped.

penalty = sum(worst 3 per rule × severity weight), score = max(0, 100 - penalty). Scores below 50 indicate significant EMC risk.

Interpreting Results

Ground plane findings — Any CRITICAL finding (signal crossing a void) is almost always a real problem. Fix unconditionally.

Decoupling findings — Distance-based findings have moderate false positive rates. A cap at 6mm may be fine for a low-speed IC but problematic for a 100MHz clock buffer. Use frequency context to prioritize.

I/O filtering — Highly relevant for cable-connected products. For board-to-board connections inside an enclosure, the risk is lower.

Diff pair findings — Protocol-specific skew limits are well-defined. USB HS (25ps), PCIe (5ps), Ethernet (50ps). Findings exceeding these limits are real issues.

PDN findings — Anti-resonance peaks are real and cause voltage droop. SPICE-verified findings are more accurate than analytical. If a peak is flagged, add a capacitor with SRF near the peak frequency.

Emission estimates — Order-of-magnitude estimates (±10-20 dB). Use them to prioritize frequency bands for pre-compliance testing, not to predict pass/fail.

EMC Standards

The --market flag maps markets to all applicable standards: us, eu, automotive, medical, military.

Limitations

• Cannot predict absolute emission levels better than ±10-20 dB
• Cannot account for enclosure effects (shielding, apertures, seams)
• Cannot predict cable radiation without knowing external cable routing
• Cannot replace full-wave simulation for complex geometries
• Cannot guarantee compliance — only accredited lab measurement can