Bus Expert - ISA Compatible

Expert knowledge for the ES-1841's system bus.

Key Specifications

Bus Signals

Control

Interrupt/DMA

• IRQ0-IRQ7: Interrupt requests
• DRQ0-DRQ3: DMA requests
• DACK0-DACK3: DMA acknowledges

Bus Cycle Timing

4 clocks = 838 ns:

T1: Address, ALE high
T2: ALE low, /RD or /WR
T3: Data transfer
T4: Deassert control

I/O Port Map

Memory Regions

Wait States

Slow peripherals insert wait states (Tw) by controlling the RDY signal.

Peripheral Interfaces

IPeripheral - Fast devices (RAM, ROM):

byte Read(uint offset);
void Write(uint offset, byte value);

IBusAwarePeripheral - Slow devices (FDC, HDD, DMA):

void Initialize(IClock clock);
void BeginBusCycle(uint offset, bool isWrite);  // Called at T1
void OnWaitState();                              // Called each Tw

Wait State Pattern

public void BeginBusCycle(uint offset, bool isWrite)
{
    _clock.SetReady(false);  // Pull RDY LOW
    _readyAtCycle = _clock.TotalCycles + 3 + waitStates;
}

public void OnWaitState()
{
    if (_clock.TotalCycles >= _readyAtCycle)
        _clock.SetReady(true);  // Release RDY HIGH
}

Formula: readyAtCycle = current + 3 + waitStates

• BeginBusCycle at T1 (cycle 0)
• +1: T1→T2
• +2: T2→T3
• +3: T3→Tw (first wait state)
• +N: Additional wait states

References

See references/ for detailed ISA bus documentation.